1. Field of Invention
The present invention relates to a method of manufacturing flash memory. More particularly, the present invention relates to a split-gate flash memory structure and a corresponding manufacturing method.
2. Description of Related Art
Flash memory is a type of memory that permits multiple read/write and erase operations. Since stored data is preserved even if power to the device is cut off, flash memory is widely used as a non-volatile memory device in personal computers and electronic equipment.
A typical flash memory unit has doped polysilicon layers to function as floating gate and control gate and a substrate. The floating gate and the control gate are separated from each other by a dielectric layer. Meanwhile, the floating gate and the substrate are separated from each other by a tunnel oxide layer. To write/erase data, a bias voltage is applied to the control gate and the source/drain region so that electrons are injected into the floating gate or the electrons are pulled out from the floating gate. To read data off the flash memory, an operating voltage is applied to the control gate so that the charge-up state of the floating gate will affect the on/off state of the underlying channel. The on/off status of the channel determines the read-out to be a logic level xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
To erase data from the flash memory, the substrate, the drain (source) terminal or the control gate is at a relatively high potential. Tunneling effect is utilized so that electrons penetrate through a tunnel oxide layer to the substrate or drain (source) terminal (that is, the substrate erase or drain (source) side erase) or pass through the dielectric layer into the control gate. However, in erasing data inside the flash memory, the quantity of electrons bled out of the floating gate during a flash memory erasing operation is difficult to control. Ultimately, too many electrons may bleed out from the floating gate leading to a state often referred to as over-erasure. Severe over-erasure may result in a conductive channel forming underneath the floating gate even without the application of an operating voltage and hence lead to erroneous read-out data. To reduce the over-erase problem, most flash memory deploys a split-gate design. A major aspect of a split-gate flash memory is that, aside from the portion over the floating gate, a portion of the control gate is lying over the substrate with a gate dielectric layer formed between the two layers. With this arrangement, a conductive channel is prevented from forming underneath the control gate so that the source/drain regions remain non-conductive and data read-out errors are minimized. However, the each split-gate unit occupies a memory cell area larger than a conventional erasable programmable read-only-memory with tunnel oxide (ETOX). Hence, the flash memory has an overall level of integration slightly below other types of memory design.
Accordingly, one object of the present invention is to provide a split-gate flash memory having a floating gate and a select gate fabricated on a trench in a substrate so that size of each memory cell is reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing split-gate flash memory. A patterned hard mask layer is formed over a substrate. A shallow trench isolation structure is formed in the substrate. Then, using another patterned mask layer as an etching mask, a trench is formed in the substrate. A tunnel oxide layer is formed over the interior surface of the trench. Thereafter, a first conductive layer is formed inside the trench. Using an etching back process, the upper surface of the first conductive layer is below the upper surface of the substrate. The hard mask layer and the exposed portion of the tunnel oxide not being covered by the first conductive layer are sequentially removed. A gate dielectric layer is formed over the first conductive layer. After an etching back process, a portion of the gate dielectric layer still remains on the first conductive layer. A conformal first dielectric layer is formed over the substrate. A second conductive layer is formed over the substrate such that the trench is completely filled. A source/drain region is formed in the substrate on each side of the second conductive layer. The first conductive layer serves as a floating gate while the second conductive layer serves as a select gate.
In the process of forming the gate dielectric layer over the first conductive layer, a conformal second dielectric layer is formed on the interior surface of the trench followed by forming a photoresist layer inside the trench. By an etching back process, the photoresist layer then partially fills the trench and exposes a large portion of the second dielectric layer. Thereafter, the exposed portion of the second dielectric layer is removed to form the gate dielectric layer on the upper surface of the first conductive layer. Hence, the gate dielectric layer is formed between the select gate and the floating gate, and at each side of the select gate by a small portion. Since the floating gate and the select gate are fabricated within a substrate trench, overall dimension of each memory cell is reduced and overall level of integration for the split-gate memory is increased.
This invention also provides a split-gate flash memory structure. The flash memory at least includes a substrate with a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench. The upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate. The select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.
In this invention, the source/drain region and the floating gate are separated from each other by a distance. When a severe over-erase condition occurs so that a conductive channel is formed underneath the floating gate before any application of voltage to the control gate, the channel on the sidewall of the select gate remains shut. Hence, the source/drain regions remain non-conductive and erroneous data read-out is prevented. On the other hand, the operation current can only flow along the drain region through select gate channel, floating gate channel, and reach the source region. Also and, due to the isolation effect from the isolation structure, the operation current cannot flow along side to cause the conduction between the source region and the drain region. In addition, since the split-gate structure is formed inside a substrate trench, dimension of each memory cell can be further reduced and overall level of integration can be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.